Logic control system including cache memory for CPU-memory transfers
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jul 17, 1984
Grant Date -
N/A
app pub date -
Sep 16, 1981
filing date -
Sep 16, 1981
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A logic control system comprised of a cache memory system and a transfer control logic unit is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system on a common communication bus to a CPU. The CPU and the transfer control logic unit communicate by way of the cache memory system with the common communication bus. In response to a CPU request to the central memory system, procedural information and instructions are requested by the transfer control logic unit from the cache memory system and presented to the CPU in such a manner as to avoid interruptions in CPU activity caused by information transfer delays.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully