Importance

Loading Importance Indicators...

Abstract

A line loop designed for the transmission of digitized voice samples as well as data words between an exchange and several subscriber terminals, not all of them necessarily equipped for voice communication, is connected through a modem to a bus with parallel branches extending to all the terminals, each branch including an outgoing-data lead, an incoming-data lead and two ancillary leads carrying clock pulses for the timing of data transmission and reception which are generated at the exchange. Each terminal, identified by a multibit address, is provided with an interface including a carrier sensor which detects the free or busy state of the line--during a time slot assigned to data transmission--on the basis of a certain protocol according to which an idle state is denoted by an unbroken succession of at least seven bits of predetermined logical value (here '1'). When a given terminal is ready to send out a message, a buffer store in the interface is enabled by the carrier sensor in the free state of the line to emit successive address bits which are compared to the instant line voltage for the possible coincidence of such a bit with a higher-priority bit ('0' in this instance) from another terminal. If so, the address emission is aborted; if there is no conflict, or if the terminal here considered prevails on every address bit, the line is seized for the transmission of the following data message to the exchange.

Loading the Abstract Image...

First Claim