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Abstract

A composite address resolution scheme is used in a distributed processing computer communications system. Many parallel processors are connected together via a multi-processor intertie bus, which serves to communicate data from any processor to any other processor. Resolution of control among several competing processors which desire access to the bus is resolved directly on the bus. The processors are online replaceable; and the system fails soft. Each processor contains resolution logic which enables simultaneous parallel resolution by any number of processors. The resolution is performed on the basis of a composite logical address (CLA) which originates within each processor. The CLA can contain non-unique priority information as well as unique logical location information. The bus is awarded to the processor exhibiting the lowest CLA. The resolution is performed starting with the most significant bit or bits and working downward towards the least significant bit or bits. The resolution for each bit or bits is delayed an appropriate period of time to enable resolution information from each processor to travel along the bus to all other processors which might be requesting access. Individual resolutions are performed by resolve elements which analyze the status of each binary bit or group of bits following translation into unitary state representation. The number of resolves can be reduced, thereby increasing the speed of the network, by means of performing resolves on two or more binary bit positions simultaneously, provided one is willing to accept added complexity.

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