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Abstract

A process for making an integrated structure comprised of complementary MOS devices is described, where electrical isolation is provided by recessed field oxide regions and by field isolation implant regions. Starting with a single conductivity type semiconductor layer, such as P- type silicon, a first masking step is used to produce an N- type well therein. After this, a layer of silicon or silicide is formed through the same mask. In a second masking step, openings are made for the field isolation implant regions. The edge of the silicon or silicide layer determines the edge of the field isolation implant, which is therefore self-aligned to the edge of the well. This same mask is later used to determine the locations of the recessed oxide isolation regions. Subsequent masking steps are used to form polysilicon gate electrodes, source and drain regions of the active devices, contact holes and contact metal and interconnects. A high density structure is provided without an extra masking step, and the conductivity levels of the well and the field isolation implants can be separately established. No additional masking steps are required for adjusting the threshold voltages of the P and N channel devices.

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First Claim