Importance

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Abstract

A dynamic signal generation circuit comprising a semiconductor circuit for receiving two input clock signals .phi. and .phi. out of phase with each other and providing a first output signal .phi.1, said first output signal .phi.1 rising in synchronism to the leading edge of said input clock signal .phi., assuming a floating state after the lapse of a predetermined period of time falling in synchronism to the trailing edge of said input clock signal .phi., and a second output signal .phi.2, said second output signal .phi.2 falling in synchronism to the occurrence of the floating state of said input signal .phi.1 and rising in synchronism to the trailing edge of said input clock signal .phi., a transistor circuit including a first and a second enhancement type transistor cascade connected between a V.sub.DD and a V.sub.SS power supply terminal, said first output signal .phi.1 from said semiconductor circuit being impressed upon the gate of said first enhancement type transistor, said second output signal .phi.2 from said semiconductor circuit being impressed upon the gate of said second enhancement type transistor, a capacitor circuit connected between the gate of said first transistor and the node between said first and second transistors, and a depletion type transistor connected between said V.sub.DD power supply terminal and said V.sub.SS power supply terminal, the gate of the depletion type transistor being connected to a point at a potential substantially same as the potential on said node between said first and second transistors.

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First Claim