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Abstract

An apparatus for distributing the control of data transfers within single instruction stream multiple data stream processors. Each of the parallel processors or arithmetic units is coupled to a dedicated local memory. A main memory provides storage of system data. Each dedicated local memory and the main memory are coupled to a bus interface unit. Each bus interface unit is coupled to a common data bus for the transfer of data between the main memory and the dedicated local memories. Each bus interface unit provides the control functions required to transfer data between the common data bus and the main or local memory to which it is coupled. One bus interface unit is designated the resource controller. The resource controller performs all of the functions of a bus interface unit and also provides the system level functions of supplying clock signals and performing bus arbitration. Each bus interface unit is capable of managing transfers to and from its associated memory thereby distributing control of the multiple data streams eliminating the potential problems associated with requiring a single controller to manage these parallel data transfers.

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First Claim