High speed data bus system

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 4481625
SERIAL NO

06313524

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Abstract

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In a high speed data bus system, each functional unit has an associated port which operates to accept all related information that makes up a communication, or if this cannot be done, to accept none of the information. More particularly, an information transfer, depending on its nature, may comprise one BIQ or more than one BIQ (a 'BIQ' is a bus information quantum which is placed on the bus for one bus cycle). To implement the indivisibility of multiple-BIQ transfers, the control logic for each port includes screening circuitry responsive to the state of the port's input buffers, and further responsive to flags from the functional unit for selectively accepting or rejecting BIQ's, and further includes screening constraint circuitry to ensure that the port accepts all or none of the BIQ's that make up the transfer. Depending on the flag, the rejection may be total, or may apply only to a designated class of transfers (for example, operations).

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION A DE CORP3065 BOWERS AVENUE SANTA CLARA CA 95052

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lau, Harlan Campbell, CA 1 185
McFarland, Jr Harold L Santa Clara, CA 3 262
Roberts, Allen W Union City, CA 5 396

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