Monolithic CMOS low power digital level shifter
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United States of America Patent
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-
Dec 4, 1984
Grant Date -
N/A
app pub date -
Jan 19, 1982
filing date -
Jan 19, 1982
priority date (Note) -
Expired
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Abstract
A CMOS digital level shifter circuit is provided which latches one transistor of a complementary transistor pair off when the other transistor of the pair is on to prevent direct current dissipation of power when the input signals to the shifter circuit are not in transition.
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