Importance

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Abstract

Apparatus is provided for delaying an electrical signal present at a selected node. The apparatus includes a first multiplexer 71 which connects one of eight inputs I.sub.0 -I.sub.7 to an output terminal 75, an adjustable length delay line 72 is coupled between each pair of input terminals I.sub.0, I.sub.7, and the input signal is then supplied to the first input terminal of the multiplexer 71. The delay lines 72 are trimmed to create the desired time delay between input terminal 74 and output terminal 75. For larger adjustments of the time delay for the signal is supplied to input terminal 74 and supplied to another terminal 78 connected to the input terminal I.sub.0 of another multiplexer 61. Logic gates 62-67 are connected between each pair of terminals I.sub.0 -I.sub.6 of the second multiplexer 61. A coarser adjustment of the time delay than achievable with the delay lines 72 is made by switching of an appropriate input terminal of the second multiplexer 61 to the output terminal 69 of the multiplexer 61. In this manner one or more gates 62-67 may be added to the path delay of the input signal supplied to terminal 74.

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First Claim