Method for simulating and testing an integrated circuit chip
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United States of America Patent
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Dec 18, 1984
Grant Date -
N/A
app pub date -
Nov 16, 1981
filing date -
Nov 16, 1981
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method and apparatus for simulating custom chips to be used in a data processing system. Each chip is simulated by a chip simulator that includes a mother board and a plurality of baby boards mounted and interconnected on the mother board. Each baby board has circuit components mounted thereon for performing the circuit function of one cell of the chip. Chip simulators are interconnected in an interconnecting apparatus that supports the mother boards in parallel and spaced apart relation. Chip simulators that represent all of the chips found on a single printed circuit board in the system are interconnected at the interconnecting apparatus so that design errors which are only evident when the chips are interconnected can be tested for and detected prior to fabrication of the chips.
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