Serial-parallel-serial charged coupled device memory and a method of transferring charge therein
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United States of America Patent
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-
Jan 8, 1985
Issued Date -
N/A
app pub date -
Oct 20, 1983
filing date -
Mar 9, 1981
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An SPS CCD memory using two phase clocking in the serial registers and ripple clocking in the parallel registers with interlacing transfer of charge in the parallel registers to the output serial registers. First alternate parallel registers are coupled to the output register through first transfer gates and first storage gates, and second alternate parallel registers are coupled to the output register through second transfer gates and second storage gates. Third storage gates are provided with each third storage gate alternately receiving charge from a first storage gate and a second storage gate with the third gate delivering the charge to the same storage element of the output register. By linearly staggering the endmost gates of the first alternate parallel registers and the second alternate parallel registers, the interlacing of charge occurs at the endmost gate of the parallel registers.
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