Microprocessor controlled phase locked loops
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United States of America Patent
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-
Jan 15, 1985
Grant Date -
N/A
app pub date -
Dec 9, 1981
filing date -
Dec 9, 1981
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A digital counter is phased locked to a reference frequency by a voltage trolled oscillator which causes the counter to increase its count rate or decrease its count rate in accordance to the presence of a one or a zero on the most significant bit of the counter at the halfway point of one cycle of the reference frequency. The counter is reset at the end of the cycle of the reference frequency. A single microprocessor which can assess this most significant bit (MSB) and vary the oscillator output, can in this manner control any number of independent phase lock loop circuits.
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