FIFO buffer to cache memory
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United States of America Patent
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-
Jan 15, 1985
Grant Date -
N/A
app pub date -
May 12, 1982
filing date -
May 12, 1982
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A minicomputer system is disclosed having a megabus with a plurality of processors and/or subprocessors, input/output (I/O) units and including logic for enabling the detection, decoding, storage and dispatching of data and instructions between the megabus and associated processors. The logic detects information addressed to its associated processors and synchronizes the transfers between the independently timed asynchronous processors and the units attached to the megabus.
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