Voltage doubler circuit

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United States of America Patent

PATENT NO 4495556
SERIAL NO

06445389

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Abstract

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A voltage ratio doubler circuit comprising an input node maintained at a constant input voltage V.sub.IN ; an output node at an output voltage V.sub.OUT ; and means, coupled between the input node and the output node, for selectively determining the ratio V.sub.OUT /V.sub.IN to equal either (a) a value K' or (b) a value K'/2 determined by impedances in the doubler circuit. In a first embodiment of the invention, the impedance of the load placed at the output node is matched with the system impedance of the doubler circuit. In this first embodiment, the input impedance, and hence the level of V.sub.IN at the input node does not vary regardless of which voltage ratio is selected. In a second embodiment, the load impedance and doubler circuit system impedance do not match. In this second embodiment, a leveller means is included. The leveller means provides a reference voltage V.sub.REF which varies with changes in input impedance at the input node. The reference voltage V.sub.REF is used to maintain V.sub.IN at a constant level. In each embodiment, the input node represents a virtual ground (at constant voltage) to the load. In the second embodiment, selecting between V.sub.OUT :V.sub.IN ratios of K' and K'/2 results in a corresponding change in the ratio V.sub.OUT :V.sub.REF between two values K and K/2. The values of K and K/2 are constants determined by the impedances in the doubler circuit and the load.

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Patent Owner(s)

Patent OwnerAddress
SIERRA NETWORKS INC485 CAYUGA ROAD - P O BOX 222 BUFFALO NY 14225

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Banning, Harmon W Derwood, MD 4 229
Patukonis, Robert J Ijamsville, MD 2 8

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