System for polynomial division self-testing of digital networks
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United States of America Patent
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Feb 5, 1985
Grant Date -
N/A
app pub date -
Jul 26, 1982
filing date -
Jul 26, 1982
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A built-in test system employs dual-mode feedback shift registers to supply test vectors and evaluate test responses of functional and interface networks of a logic system. Test responses are supplied to a quotient bit compressor which generates a system response signature for comparison with an expected fault-free signature to produce a system pass/fail status signal.
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