Signal transfer timing control using stored data relating to operating speeds of memory and processor
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United States of America Patent
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-
Feb 12, 1985
Grant Date -
N/A
app pub date -
Dec 9, 1981
filing date -
Dec 17, 1980
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A memory controlling apparatus retains time information prepared based on performance of a memory and a processor, and determines timing of signal exchange between the memory and the processor based on the time information. An access time to the memory is reduced while maintaining a flexibility to a change of the access time due to increase of memory capacity or reconfiguration of the memory.
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