Bidirectional data byte aligner
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United States of America Patent
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-
Mar 26, 1985
Grant Date -
N/A
app pub date -
Nov 1, 1982
filing date -
Nov 1, 1982
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A byte-addressable memory system having an array of transceivers with control logic which enables memory to be addressable on individual byte boundaries rather than on two byte (word) or four byte (longword) boundaries. The memory system has two independent even-address and odd-address segments allowing parallel access to two longwords (eight bytes or one quadword) simultaneously. Logic determines which of the eight bytes should be placed on a four byte bus and the sequential order of the bytes on the bus. The entire operation takes place in one memory cycles time period and can start at any byte address.
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