Associative processor with variable length fast multiply capability
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United States of America Patent
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Mar 26, 1985
Grant Date -
N/A
app pub date -
Aug 2, 1982
filing date -
Aug 2, 1982
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An associative processor is described wherein an array of associative processing cells is configured to achieve variable length multiplication of numbers, such as binary two's complement numbers, under mask control. A configuration suitable for signal multiplication is described wherein the processing sequences in all cells are compatable, each to the other, whether the cells are at the edges or the middle of an array row, and regardless of the computational sequences required to be performed. An associative cell structure is described, including an improved arithmetic logic unit having separate carry and borrow save paths which may be enabled and active simultaneously or alternately.
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