MOS Analog switch driven by complementary, minimally skewed clock signals
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United States of America Patent
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-
Apr 2, 1985
Grant Date -
N/A
app pub date -
Feb 10, 1983
filing date -
Feb 10, 1983
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An MOS analog switch utilizing two transmission gates which are compensated by a third transmission gate is provided. The transmission gates may be either single or complementary conductivity type transmission gates and are controlled by complementary clock signals. A method and apparatus for minimizing clock skew thereby reducing error voltages caused by parasitic capacitance are provided.
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