Importance

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Abstract

The application relates to an interlace detector for a raster beam control circuit, such as in a television or computer display. Under 1:1 interlace conditions, depending on the condition of the logic at the time that the 1:1 interlace is selected, an odd field condition may result wherein the first half of the top horizontal line and the second half of the bottom horizontal line are blanked. The interlace detector detects this situation by detecting coincidence between a horizontal blanking pulse and the vertical reset pulse, and delays the transmission of the vertical reset pulse to the vertical field counter for one-half of the horizontal line scan time. This, in turn, delays vertical blanking so that a full line of information appears in the upper and lower lines of the display. In the specific embodiment disclosed, a bistable circuit triggered by horizontal blanking pulses and the undelayed vertical reset pulse produces the delayed vertical reset pulse.

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First Claim