Importance

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Abstract

A semiconductor memory device contains an on-chip self-incrementing counter which may be loaded from address input terminals, so that the memory cell array may be accessed using either an incoming address or the last address incremented by one. Also, the incremented last address is saved in a latch. A comparator receives the present address and incremented last address, and if these match a data output is available immediately. After a read cycle, the array is always accessed using the incremented last address, so when another fetch is initiated from the CPU, if it is for the next sequential address, the data is already available in a data ouput latch and the apparent access time is much less than that of the memory array.

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First Claim