Importance

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Abstract

A high speed countdown counter (FIG. 7) capable of operation at up to 10 MHz is provided which comprises a number of stages each comprising a flip flop (134, 136; 144, 146; etc.), a preset data input (IN1, IN2, etc.), a carry input (N11, N10, etc.), a data output (N5, N4, etc.), and a carry output. Dynamic Depletion Mode (DDM) transistors (129, 139, etc.) are employed to reduce charging time at inter-stage nodes and thereby improve speed, while minimizing circuit size and power requirements. A look-ahead feature enables early detection of an 'all zero minus one' count and enables the presetting of data into the counter simultaneously with the generation of a 'carry out' signal from the counter. Various internal counter control signals are delayed by couplers driven by a two-phase non-overlapping clock, in order to allow for signal propagation time through the corresponding circuit elements.

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First Claim