Importance

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Abstract

Surge-current that occurs when the pair of input lines of a power supply are energized is limited by connecting the source-to-drain path of an insulated gate FET in series in one input line and connecting its gate to an intermediate node of a voltage divider that is connected across the input lines, with an integrating capacitor connected between the node and one input line for reducing the rate of conduction of the FET. Overvoltage protection is provided by electrically connecting a latch circuit between the node and the one input line, with the FET's gate being electrically connected to the collector of a latch transistor that has its base driven by an overvoltage indication. The series combination of a timing resistor and timing capacitor is connected across the primary conduction path of the FET and the base of a unijunction transistor that has its emitter directly connected to the junction of the resistor and capacitor and AC coupled to the base of the latch transistor. A prescribed time interval (set by charging the timing capacitor to the trigger voltage of the unijunction) after the latch is set by an overvoltage condition, the unijunction fires for discharging the timing capacitor and resetting the latch, and thus the power supply.

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First Claim