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Abstract

A bus system architecture and method provides on a substrate a bus line system for first and second circuit boards designed to extend across the substrate. Individually dedicated first, second and third bus lines for the first circuit boards are provided in a first bus line array at one side of the substrate. Individually dedicated fourth, fifth and sixth bus lines for the second circuit boards corresponding, respectively, to the first, second and third bus lines, are provided in a second bus line array representing a mirror image of the first bus line array at an opposite side of the substrate. An area of the substrate between the first and second bus line arrays may be subdivided into sequential first and second regions adjacent the first bus line array, and sequential third and forth regions adjacent the second bus line array. A third bus line array is located in the first region for the first circuit board, and a fourth bus line array in the fourth region for the second circuit boards. Individual connectors may be provided in the second and third regions for the second and first circuit boards, respectively. A microprocessor system that may be combined with the bus system architecture has a first microprocessor controlling a second microprocessor and various peripherals, such as via one of the above mentioned bus line arrays, and has the second microprocessor control further peripherals, such as via another bus line array.

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