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Abstract

A high speed processor for a digital modem which transmits and receives data over voice grade telephone lines, for performing logical addition and subtraction operations during encoding and decoding of data as phase shift keyed modulation. A quarter square multiplying circuit is provided which executes multiplying operations at high speed. A discrete-input multiplexer is provided and controlled to bring single-bit variables into the processor as word variables permitting logic operations to be performed rapidly and efficiently. A bitwise logic circuit is provided in conjunction with the multiplexer and the processor to perform logic operations on bit pairs within the same word or on pairs of bits from different locations in two different operands. An interrupt subsystem includes a toggle circuit which alternately monitors for transmit and receive interrupts.

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First Claim