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Abstract

A method for fabricating an integrated circuit semiconductor device comprised of an array of MOSFET elements having self-aligned or self-registered connections with conductive interconnect lines. The method involves the formation on a substrate of a thick oxide insulation layer surrounding active area openings. A gate electrode within each opening is utilized to provide self-registered source and drain regions. In two embodiments, the gate is covered on all sides and on its top surface with a protective layer of nitride or thick oxide. In one of the embodiments, after the formation of the source-drain regions a relatively thin protective layer of etch stopper is applied to the entire chip prior to the application of an upper insulative layer. When oversized windows are etched in the upper insulative layer, the etch stopper layer prevents etching of the nitride layer, thus preventing shorts or leaks between conductive and active areas and providing self-aligned contacts with minimum spacing from adjacent conductive areas. In another of the embodiments, a thick layer of oxide provides insulation between the gate, source-drain region and conductive lines. Two other embodiments teach novel methods of forming thick oxide protective layers for the gate sidewalls. With these methods, additional internal protection over prior art devices is provided in MOS devices with source-drain regions formed either by diffusion or ion implantation.

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First Claim