Apparatus for controlling writing of data into a memory having different read and write times
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United States of America Patent
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-
May 28, 1985
Grant Date -
N/A
app pub date -
Apr 20, 1983
filing date -
Apr 22, 1982
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An apparatus for controlling the writing of data from a processor into a memory having different read and write times, wherein the memory is connected directly to the processor through address and data buses without the use of an input/output port. A timer circuit is connected to the buses and memory and is controlled by the processor to produce a write timing signal which controls the writing of data into the memory. The processor is placed in a holding state, based on the write timing signal, for a period long enough to assure that the data will be written into the memory in its entirety.
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