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Abstract

A digital processing device fabricated on a single semiconductor substrate includes an electrically programmable memory, a random access memory, a central processing unit, all connected by an information transfer bus. An external interface is provided connected to the information transfer bus to provide information contained on the bus to external devices. At least one security bit is provided to determine the status of data stored in the nonvolatile memory and portions of the random access memory. An external interface inhibit circuit is connected to the external interface. Address logic is connected to the information transfer bus to determine when information contained in the electrically programmable memory or the random access memory is being accessed. The address logic also determines the security status of information stored in the selected portions of the random access memory and the electrically programmable memory. In addition, the address logic is connected to the central processing unit to determine when an instruction operand is being fetched. The address logic is also connected to the external interface inhibit circuit to inhibit the operation of the external interface when an instruction operand is being fetched from the electrically programmable memory or selected portions of the random access memory.

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First Claim