Bus selection control in a data transmission apparatus for a multiprocessor system
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jun 11, 1985
Grant Date -
N/A
app pub date -
Apr 8, 1982
filing date -
Apr 10, 1981
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
In a multiprocessor system having a main memory and a plurality of processors connected through common address bus, data bus and answer bus for data transfer, a data transmission apparatus is provided for each of the main memory and the processors and includes bus request control lines for transferring bus request signals and bus control signals, and a bus controller for separately controlling selections of the address bus, the data bus and the answer bus in response to the signals on the bus request control lines and the request signal. Overlapped processing such as data write and data write answer or data read and data read answer in one cycle is possible.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully