Importance

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Abstract

A high speed arrangement for detecting the occurrence of a flag character in a stream of serial digital data signals employs a pattern register in which are stored the bits of the referene flag pattern. As each bit of the serial data is received, it is simultaneously compared by a set of comparators with each of the bits in the flag pattern. The first comparator of the set compares the data bit with the first bit of the flag pattern and each successive comparator compares the data bit with the next successive bit in the pattern. The outputs of the comparators are coupled to corresponding stages of a shift register in the same ordered sequence as the comparators. All the stages of the shift register are arranged to be simultaneously clocked by clock signals. Each stage of the shift register is coupled to the next stage by a gate that permits the shift of a logic bit from the preceding stage to the succeeding stage only when the preceding stage was previously set by a signal from a comparator indicating the occurrence of a match between a data bit and a pattern bit and the gate receives a signal from the next comparator in the set indicating the occurrence of a match between the next data bit and the next pattern bit.

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First Claim