Biased current mirror having minimum switching delay
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United States of America Patent
Stats
-
Jun 25, 1985
Grant Date -
N/A
app pub date -
Feb 7, 1984
filing date -
Feb 7, 1984
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A biased current mirror comprises first and second transistor having their emitters connected to ground and their bases connected together. The collectors of the transistors are connected to connector pads on an integrated circuit. Bias current is supplied to the input of the current mirror to keep the base-emitter capacitances of the transistors charged despite a cutoff of input current. An offset current, proportional to the bias current is supplied to the output of the current mirror to offset the output current response of the mirror to the bias current. A current-capacitance oscillator including two biased current mirrors comprises differentially coupled pairs of transistors with the biased current mirrors controlling the charge and discharge of a timing capacitor. A conventional phase detector circuit incorporates a biased current mirror to minimize switching error due to delays associated with junction capacitors of the transistors.
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