Simulator system for logic design validation
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United States of America Patent
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Jul 2, 1985
Grant Date -
N/A
app pub date -
Oct 22, 1982
filing date -
Oct 22, 1982
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A hardware network or system is disclosed for testing LSI and VLSI logic device design and system design by simulation utilizing individual gate functions. The simulator system uses switching logic, random access memory, and a state table device to simulate particular test routines to test device design with functions which may appear in random or semi-random sequence.
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