Processor-addressable timestamp for indicating oldest written-to cache entry not copied back to bulk memory

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United States of America Patent

PATENT NO 4530054
SERIAL NO

06354556

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Abstract

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In a data processing system including a processor, a bulk memory, a cache, and a storage control unit for controlling the transfer of data between the bulk memory and the cache, a timestamp is generated with each write command. A linked list is maintained, having an entry therein corresponding to each segment in the cache which has been written to since it was moved from the bulk memory to the cache. The timestamp accompanying a write command which is the first command to write to a segment after that segment is moved from bulk memory to the cache is entered into the list at the most recently used position. An entry in the linked list is removed from the list when the segment corresponding thereto is transferred from the cache to the bulk memory. The linked list is utilized to update a value TOLDEST, which represents the age of the oldest written-to segment in the cache that has not been returned to bulk memory since it was first written to. The processor periodically issues a command which transfers TOLDEST from the subsystem to the processor. In case of a cache failure, such as might result from a power loss, the processor may sense the latest value of TOLDEST together with other file recovery synchronization information and determine what part of the data which it sent to the cache was lost because it did not get recorded in the bulk memory.

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Patent Owner(s)

Patent OwnerAddress
SPERRY CORPORATION A CORP OF DE1290 AVENUE OF THE AMERICAS NEW YORK NY 10019

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hamstra, James R Plymouth, MN 27 937
Swenson, Robert E Mendota Heights, MN 19 1319

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