Solid state three dimensional semiconductor memory array
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United States of America Patent
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-
Aug 13, 1985
Grant Date -
N/A
app pub date -
Jun 3, 1982
filing date -
Jun 3, 1982
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A memory circuit including several semiconductor substrates, each containing addressable memory elements, address receiving circuitry for receiving address signals and for providing data from the memory in response to the address signals, control circuitry for receiving control signals and for controlling the reading and writing of the memory elements, and interconnection circuitry including elevated portions of the semiconductor substrate connected to contact paths of the semiconductor substrate located above to provide electrical continuity between the addressable circuits of each semiconductor substrate and electrical continuity between the control circuits of each semiconductor substrate.
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