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Abstract

A clock wave is synchronized to the frequency of serial binary data bits. Digital circuitry derives a clock wave by responding to the data bits to selectively (a) increment a reference frequency, (b) decrement the reference frequency, and (c) not change the reference frequency. The digital circuitry divides each data bit into an even number of sub-bits. The binary value associated with a first half of the divided sub-bits of a particular data bit is compared with the binary value associated with a second half of the divided sub-bits of the particular data bit. In response to the derived clock wave and the comparison, the reference frequency is derived, incremented or decremented. The frequency of the source is respectively incremented and decremented in response to first and second relations of the binary value associated with the first half relative to the binary value associated with the second half. The frequency of the source is not changed when the binary values associated with the first and second halves are equal.

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