Importance

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Abstract

A coordinate data memory is provided, in which a plurality of coordinate data representing partial patterns constituting a pattern to be drawn on a semiconductor wafer are stored. The coordinate data are supplied from the coordinate data memory to a plurality of coordinate data converters. The data converters convert coordinate data into address data by which pattern memories are specified respectively. Bit patterns are formed according to the address data in the pattern memories, respectively. The bit patterns of the pattern memories are synchronously read out bit by bit and synthesized in a logic gate circuit, and the resultant pattern is supplied to a blanking circuit bit by bit.

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First Claim