Static memory having load polysilicon resistors formed over driver FET drains
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United States of America Patent
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-
Sep 10, 1985
Issued Date -
N/A
app pub date -
Jan 19, 1984
filing date -
Sep 19, 1979
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A semiconductor device having a semiconductor substrate, wherein first and second insulating gate FET transistor connected respectively in series with first and second polycrystalline silicon layers acting as loads of first and second inverters are formed. The first polycrystalline silicon layer is provided above the drain of the first insulation gate FET transistor, and the second polycrystalline silicon layer is provided above the drain of the second insulation gate FET transistor.
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