Internal communication arrangement for a multiprocessor system

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United States of America Patent

PATENT NO 4543627
SERIAL NO

06330171

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A data communication arrangement in which an interface processor effects the transmission of messages between two processors of a multiprocessor system. The interface processor is connected to the communicating processors via direct memory access circuits. A sending processor stores messages in a send buffer in memory of the sending processor and controls a pointer in that memory indicating the loading of message into that buffer. The interface processor reads this pointer and the messages, and writes a pointer and the messages in a receive buffer of a receiving processor. The interface processor limits the loading of new messages into the send buffer by delaying the updating of an unload pointer, creating memory space for new messages, until the receiving processor has processed the transmitted messages. Messages can also be used to initiate the transfer of a block of data from the memory of one processor to that of another. Initialization of the interface processor is a joint effort of the communicating processors.

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Patent Owner(s)

Patent OwnerAddress
BELL TELEPHONE LABORATORIES INCORPORATED600 MOUNTAIN AVENUE A CORP OF NY MURRAY HILL NJ 07974-2070

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Schwab, Thomas F Lisle, IL 1 69

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