Bus for data processing system with fault cycle operation
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United States of America Patent
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-
Sep 24, 1985
Grant Date -
N/A
app pub date -
Jan 28, 1983
filing date -
Jan 28, 1983
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A digital data processing system including a number of input/output units that communicate with a memory over an input/output bus and through an input/output interface. The input/output interface pipelines data transfers between the input/output units and the memory. The interface includes an incoming and outgoing buffer for queuing requests from the input/output units, and transfers from the memory. In the event of an error in the input/output interface's pipeline buffer, the interface transmits, by means of a fault cycle over the bus, information to the input/output unit that initiated the transfer unit to enable it to recover.
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