Process for positioning an interconnection line on an electric contact hole of an integrated circuit
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United States of America Patent
Stats
-
Oct 1, 1985
Grant Date -
N/A
app pub date -
Mar 16, 1984
filing date -
Mar 18, 1983
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
The invention relates to a process for the positioning of an interconnection line on an electric contact hole in an integrated circuit. According to the invention, one or more conductive layers forming a conductive covering are deposited on the complete integrated circuit. The first conductive layer is deposited by an isotropic process. The interconnection line to be produced is then masked by a resin layer, followed by the successive etching of each conductive layer. Finally, an overetching of these conductive layers is effected in the electric contact hole, followed by the elimination of the resin.
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