Programmable counter system

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United States of America Patent

PATENT NO 4545063
SERIAL NO

06497136

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Abstract

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A programmable counter system of the swallow operation type using binary counters is disclosed. The counter comprises a prescaler for frequency dividing an input signal by a frequency division factor '2.sup.n -1' or '2.sup.n ', upper and lower order bit counters for counting down an output signal from the prescaler, a flip-flop for selecting either the frequency division factor '2.sup.n -1' or '2.sup.n ' according to the logical level of the output signal of the counter A or B, and inverters for level inverting programming data and applying them to the lower order bit counter A, thereby setting a division number of the counter A to a complement of the binary code of the programming data.

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Patent Owner(s)

Patent OwnerAddress
TOYKO SHIBAURA DENKI KABUSHIKI KAISHA72 HORIKAWA-CHO SAIWAI-KU KAWASAKI-SHI

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kamimaru, Nobuyuki Yokohama, JP 3 47

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