Importance

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Abstract

A microcontroller for controlling a digital device which controller is formed of a plurality of control stores each of which is provided with a register counter to address different locations within corresponding control store. Each control store is accessed each clock cycle and an instruction register is provided to receive one of the fetched microinstructions from the selected control store. In this summer, a microinstruction is presented to the instruction register each clock cycle even though the previous microinstruction was a conditional branch, a jump to subroutine or a return to subroutine instruction. In order to accommodate jump to subroutine and corresponding return from subroutine instructions, the respective address of the return subroutine is stored in a push-down stack for presentation to a selected one of the above-referred-to register counters in an order the reverse of the order in which those addresses were placed on the top of the stack.

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First Claim