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Abstract

A delay circuit including an even number of memory devices, for example two, reading from one memory device, while writing to the other. Sequences of bit addresses are generated for writing and reading, with an offset between the sequences. For the case of two memory devices, each address sequence is applied alternately to the one and then the other memory device. Importantly, if each memory device has an even number n of storage locations, then, preferably, only (n-1) of these are used in the generated sequences of addresses. This has the result that the circuit can write to and read from all of the memory locations in the memory devices. Thus, the maximum delay possible in the circuit of the invention is nearly the total number of bits in the multiple memory devices, and the circuit is capable of handling data at the maximum operating rate of the memory devices.

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First Claim