Importance

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Abstract

An improved memory management system is described having particular application for use in computer systems employing virtual memory techniques. The system includes a CPU and other data processing devices, such as I/O devices, direct memory access (DMA) units, a system bus, etc., which are coupled to a 'virtual' address bus for transferring virtual address information to a main memory unit (MMU). Access to the virtual bus is controlled by arbitration unit in order to insure that only a single device may communicate with the MMU at a time. In a preferred embodiment, address space within the MMU is allocated into a plurality of memory spaces, each space including translation data for use by a particular data processing device coupled to the virtual bus. A device gaining access to the virtual bus identifies the particular MMU memory space to be used for its address translation by providing unique context bits denoting the memory space to the MMU.

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First Claim