Importance

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Abstract

Circuitry for decoding differential phase shift keyed signals utilizes a counter, having a capacity selected such that in an integration interval having a duration equivalent to one-half the period of a reconstructed carrier, a full count and resultant rollover identifies a decision threshold for information descriptive of the received signal. At the conclusion of the integration interval, the contents of the counter represent half a full count thereof for no phase error in the reconstructed carrier. Phase error in the carrier is determined during a subsequent interval by counting up of the same counter to achieve a reset condition thereof. The counter is counted up until occurrence of a rollover signal, which signal is used to prevent passage of any further pulses to the counter and to maintain the counter in an all zero state. At the input, a hard limited version of the modulated signal is provided to an EXCLUSIVE OR gate together with the reconstructed carrier in order to provide decoding intervals for counting of clock pulses by the counter during the preset integration intervals.

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First Claim