Importance

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Abstract

Telephone system interface circuitry for regulating the full duplex exchange of asynchronous serial bit signal information between the system's station equipment and central equipment matrix switch includes a central equipment signal processor, central equipment master clock, and individual central equipment signal ports for each station, and includes in each station equipment variable time delay transmission circuitry responsive to the signal information transmitted periodically from the central equipment for transmitting station information at the same periodic interval but delayed from the received central signal information by a delay time interval selected to regulate the actual time of arrival (TOA) of the station information at the associated central port coincident with a desired TOA for that port.

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First Claim