Importance

Loading Importance Indicators...

Abstract

A multiprocessor computer system wherein memory buses of separate central processing unit systems are interfaced to an intermemory communication network for transfer of data between memories of said separate central processing unit systems. The intermemory communication network includes a plurality of preferably passive intermemory communication links being tapped for connection to link adapters interfacing a number of central processing unit systems to each intermemory communication link. The number of central processing unit systems may be different for different intermemory communication links. The memory buses are configurated to allow for direct data transfer between any memory fraction of a common memory shared by at least two central processing unit systems without interfering with the central processing units such that the data transfer is controlled by direct memory access control means. The multiprocessor computer system includes separate configuration controllers being effective to reconfigurate the overall system in the event of failure. The reconfiguration comprises switching of fractions of memory between the memory buses of at least two central processing unit systems. At least one of the memory fractions is directly addressable by a respective peripheral processor. Also, one of the peripheral processors backs up the others to obtain N+1 redundancy.

Loading the Abstract Image...

First Claim