Dynamic memory with high speed nibble mode
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 28, 1986
Grant Date -
N/A
app pub date -
Jul 8, 1983
filing date -
Jul 8, 1983
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A semiconductor dynamic memory device has an array of one-transistor cells, with row and column decode to produce a 4-bit wide input or output. Single-bit data-in and data-out terminals for the device may be coupled to the 4-bit array input/output in a sequential mode. The row and column addresses are latched when RAS and CAS drop, and this includes the address of the starting bit within the 4-bit sequence. The other three bits follow as CAS is cycled. This starting address is used to set a bit in a 4-bit ring counter, which is then used to cycle through the sequence.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully