Self booting logical AND circuit
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United States of America Patent
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-
Feb 11, 1986
Grant Date -
N/A
app pub date -
Jan 17, 1983
filing date -
Jan 17, 1983
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A solid state logical 'AND' circuit implementation in NMOS circuitry has clock pulse conditioning providing self booting voltage levels for ultra fast propagation times and minimal power dissipation, where memory row driver concepts are utilized and silicon area is minimized, and two, low impedance, non-overlapping clock pulses, normally present in the environment are utilized.
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