Data processor having multiple-buffer adapter between a system channel and an input/output bus
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United States of America Patent
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Feb 18, 1986
Grant Date -
N/A
app pub date -
May 13, 1983
filing date -
May 13, 1983
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A data processor has a block-multiplexed system channel coupled to a processing engine and a byte-multiplexed bus coupled to multiple I/O devices. A multi-buffer adapter transfers data by cycle-steal (direct memory access) operations between the channel and the bus. The adapter has multiple buffers switchable to the channel in a burst mode by a channel interface and to the bus in a byte mode by a device-level interface.
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